1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more specifically to a semiconductor integrated circuit having a multi-level interconnection structure and an interlayer film formed by coating an organic solution of a silicon compound.
2. Description of Related Art
In the semiconductor integrated circuit, in the prior art, an increase of integration density in a semiconductor manufacturing process is indispensable to increase the number of circuit elements and to reduce the size of an integrated circuit chip. In order to satisfy this demand, various approaches have been proposed. As one of the proposed approaches, a multi-level interconnection structure has been known as a means which can relatively simply achieve the high density. In this multi-level interconnection structure, the larger the number of interconnection levels is, a concavo-convex occurs in interlayer insulating films, with the result that a microminiaturization of interconnection comes to have a limitation, and there occur various obstacles including disconnection of the interconnection at a step and a shortened lift of interconnection. As a result, reliability of the semiconductor integrated circuit drops. Therefore, it is important to simultaneously realize both microminiaturization of interconnection and planarization of the interlayer insulating films.
The planarization technique includes a method for coating a SOG (spin-on-glass) solution between first level and second level aluminum layers in the case of a double-layer aluminum process. A coating of the SOG solution can be carried out by various methods depending upon the semiconductor device manufacturing process. For example, in one typical method, after formation of an interlayer insulating film, a wafer is rotated about a center of the wafer, and the SOG solution is dropped from an upper position, so that the SOG is distributed throughout the wafer by action of a centrifugal force of the rotation. Thereafter, the wafer is heat-treated to evaporate an organic solvent of the SOG solution and to advance the dehydration and polymerization of the silicon compound, so that a silicon oxide film is formed. Furthermore, the SOG silicon oxide film thus formed to cover the whole surface of the wafer is etched back to remove an unnecessary silicon oxide film, so that only recesses in the interlayer insulating film between the first level and second level aluminum layers are filled with the SOG silicon oxide film. Thus, the planarization is completed.
In ordinary cases, in a scribing line area or in the neighborhood of the scribing line area on the wafer, a substrate interconnection is formed at the level of a first level or lower level interconnection layer, and is connected to the semiconductor substrate through a predetermined contact so that a substrate potential is supplied to the substrate. The substrate interconnection is formed to depict a closed loop completely surrounding a chip inner region of each semiconductor integrated circuit chip. In the periphery of each chip, therefore, a dam is built because of the thickness of the substrate interconnection layer. Because of this construction, when the SOG solution is coated by the centrifugal force of the rotation, the SOG solution deposited on portions other than the recesses is not completely escaped since it is blocked by the dam, with the result that the silicon oxide film formed by coating the SOG solution is upheaved in the proximity of the substrate interconnection.
Now, a specific example will be described with reference to FIGS. 9 and 10. FIG. 9 is a diagrammatic enlarged plan view illustrating the location of a lower level substrate interconnection in a semiconductor chip 5, in the prior art, and picked up from many semiconductor chips formed in a semiconductor wafer 19 as shown in FIG. 1. FIG. 10 is a diagrammatic partial sectional view of a substrate interconnection portion of the prior art semiconductor chip, where the SOG silicon oxide layer is deposited thickly.
In this semiconductor chip 5, as shown in FIG. 9, a lower level substrate interconnection 6 formed at the level of a first level interconnection layer, is formed to depict a closed loop completely surrounding the chip inner region of the semiconductor chip 5, at an inside of a scribing line area 8 provided along a peripheral edge of the semiconductor chip 5. As shown in FIG. 10, the lower level substrate interconnection 6 is formed to extend from the surface of the semiconductor substrate 9 to the top of a step which is formed of a field oxide film 11 and an interlayer insulating film 12 formed thereon. In the scribing line area 8 or in the neighborhood of the region 8 in this semiconductor chip 5, as shown in FIG. 10, the lower level substrate interconnection 6 formed at the first level of the interconnection layer, is connected to a diffused layer 17 formed at the surface of the semiconductor substrate 9 at a contact 10 between the lower level substrate interconnection 6 and the semiconductor substrate 9, for the purpose of supplying a predetermined substrate potential to the semiconductor substrate 9.
Another interlayer insulating film 13 is formed to cover the lower level substrate interconnection 6 and the interlayer insulating film 12. As a result, steps are generated not only in the proximity of the scribing line area, but also on the surface of the interlayer insulating film 13 because of the thickness of the interconnection layer, depending upon whether or not the first level interconnection layer exists on the interlayer insulating film 12. In order to fill the recesses created by the steps, the SOG solution is coated and dried for planarization.
In the prior art semiconductor integrated circuit mentioned above, after the SOG solution is coated, the heat treatment is carried out to form the silicon oxide film 14, and then, an unnecessary portion of the silicon oxide film is etched back. In this etching-back process, if the silicon oxide film is etched back to the degree that the recesses created by the steps are just filled with the SOG silicon oxide film, the SOG silicon oxide film 14 remains on the upheaved portion of the interlayer insulting film 13 caused by the thickness of the interconnection layer 6 under the second layer interlayer insulating film 13, as shown in FIG. 10. Thereafter, a third layer interlayer insulating film 15 is formed on the SOG silicon oxide film 14, and a through-hole contact 7 is formed to reach from the surface of the interlayer insulating film 15 to the lower level interconnection layer 6, for the purpose of connecting a second or upper level interconnection layer 4 to be formed after the formation of the SOG silicon oxide film, to the first or lower level interconnection layer 6 formed before the formation of the SOG silicon oxide film. In this through-hole contact 7, a contact face 18 generates between the upper level substrate interconnection filling the through-hole 7 and the SOG silicon oxide film 15.
After the wafer 19 is cut off along the scribing line area 8 into individual semiconductor chips and each of the individual semiconductor chips is mounted on a lead frame or the like and encapsulated by a molding resin into a product, when moisture enters from an ambient atmosphere at the outside of the semiconductor integrated circuit through a boundary between the molding resin and the lead frame, the moisture is absorbed from the scribing line area 8 to the SOG silicon oxide film 14, to enter the inside of the semiconductor chip 5. At this time, if the contact face 18 has generated, the moisture absorbed to the SOG silicon oxide film 14 reaches through the contact face 18 to the lower level interconnection layer 6 to corrode the lower level interconnection layer 6. Further, with elapse of the time, this corrosion reaches the upper level interconnection layer 4 through the through-hole contact 7. In a worst case, the contact 10 between the lower level interconnection layer 6 and the semiconductor substrate 9 becomes an insulating condition, with the result that the semiconductor integrated circuit becomes inoperable.